Education:

 

-   Phd in Computer Eng., NC State University., 2005-2010

-   MSc in Computer Eng., Sharif Univ. of Tech., 2002-2004 pdf

-   BS in Computer Eng., IAUCTB, 1997-2002

 

Employment:

 

-   Internship, Intel , Hudson, MA, July-Oct. 2010 ;

 

Research on the interaction between smart cache replacement and task placement policies in multi-cluster CMPs.

 

 

-   Internship, Qualcomm Inc., Cary, NC, Feb.-Aug. 2008 ;

 

Power modeling of the Scorpion processor based on performance monitors and characterizing the AXI bus behavior.

 

-   Research assistant, ECE Department, NCSU,  2005-2010 ;

 

Studying approaches to enable code to be executed by a better suited processing element through exploitation of the multi-core trend

 

-   Research assistant, School of Computer Science, Inst. for Studies in Fundamental Science, 2003-2005;

 

Performance evaluation and modeling of different topological structures for multicomputer systems under different switching techniques and routing algorithms

 

-   Research Engineer, Research Organization for Science & Technology (IROST), 2001-2002;

 

The complete design and implementation of the controller in a chemical fermentation system based on the i80196  microprocessor (logic, schematics and PCB design, programming and debugging)

 

Participation in the design of an AC motor PID control system based on the i80196  microprocessor.

 

Complete hardware design, IO interfacing and software implementation of IO value translation and calibration in the implementation of an AC motor control system based on a non-PID computational core (implemented on the TMS-320 DSP).

 

Instructing & Lecturing: 

 

Sharif University of Technology,

     Computer Architecture Lab Conductor (Fall & Spring 2003) 

 

University of Science & Technology,

     Lecturer of complete course on Advanced Microprocessors (Fall 2004)

 

Selected Publications:

 

 - H. H. Najaf-abadi, N. K. Choudhary, E. Rotenberg, “Core-Selectability in Chip Multiprocessors”, In Proceedings of the Conference on Parallel Architectures and Compilation Techniques (PACT), 2009.

 

- H. H. Najaf-abadi, E. Rotenberg, “Configurational Workload Characterization”, Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), 2008.

 

- H. H. Najaf-abadi, E. Rotenberg, “Architectural Contesting“, in Proceedings of the International Symposium on High Performance Computer Architecture (HPCA), 2009.

 

- H. H. Najaf-abadi, H. Sarbazi-azad, “An accurate combinatorial model for performance prediction of deterministic wormhole routing in torus multicomputer systems“, Proceedings of International Conference on Computer Design (ICCD), 2004.

 

- H. H. Najaf-abadi, “A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline“, Proceedings of the IEEE/ACM Aisa South Pacific Design Automation Conference (ASP-DAC), 2004