XP-Scalar© is a design-space exploration framework for superscalar processors.

Note: This effort is being expanded in a more comprehensive endeavor named The Fabscalar Project. You can join the Fabscalar google group to gain access to a beta version of a synthesizable superscalar model, multi-port memory model, functional simulator, and superscalar design-space exploration tool -- enabling high-fidelity design-space exploration (as apposed to the use of CACTI in XP-Scalar).

The tool currently supports variation in L1 and L2 cache configurations, issue-queue size, ROB/register-files size, LSQ size, processor width and clock frequency. The exploration tool requires symbolic links to the sim-mase simulator and the CACTI modeling tool (V4.0) to be in the same directory.

Note: this tool is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License version 2.1 published by the Free Software Foundation.

Exploration Results

The XP-Scalar framework is being used in a continual process to explore the superscalar design space of different widely used benchmarks under different design constraints and technology characteristics.

The following links dynamically display the customized microarchitectural configuration so far attained for different benchmarks. Click on link to observe results:

NOTE: Please return in the coming months to observe the outcome of the continuation and expansion of this exploration task.